Recently, the range of potential applications for EEPROMs (Electrically Erasable and Programmable Read Only Memory) has been increased as manufacturers have begun using them as memory modules for storing programs or data in cellular phones, portable information terminals, and the like. Since a relatively high voltage of ten to twenty volts is required for writing and deleting the data in an EEPROM, it is necessary to use a charge pump type booster circuit to boost a power supply voltage (typically several volts) in a positive direction.
FIG. 5 shows a conventional charge pump type booster circuit for obtaining a higher potential booster voltage.
In the conventional, prior art circuit, a charge pump type booster circuit 21 is provided with a driver circuit 22, a charge pump series 23, and a control circuit 24.
The driver circuit 22 is provided with CMOS drivers 25, 26. The driver 25 comprises a PMOS transistor DP1 and an NMOS transistor DN1 connected in series between a power supply VDD (power supply voltage VDD) and a ground or reference potential. A control signal a-1 is transmitted to a gate of transistor DP1, while a control signal a-2 is transmitted to a gate of transistor DN1. Moreover, the driver 26 comprises a PMOS transistor DP2 and an NMOS transistor DN2 connected in series between the power supply VDD and ground. A control signal b-1 is transmitted to a gate of transistor DP2, while a control signal b-2 is transmitted to a gate of transistor DN2. Additionally, the control signals a-1, a-2, b-1, b-2 are generated by the control circuit 24.
The n stages (n being an integer) of the charge pump series 23 are provided with NMOS transistors T1 to Tn as n switching elements connected in series, n capacitors C1 to Cn, and NMOS transistors TD1 to TDn. Additionally, the m-th stage in the charge pump series 23 (m being an integer smaller than n) comprises NMOS transistor Tm and capacitor Cm, and a source of NMOS transistor Tm forms a node Nm. An output voltage HVOUT of the charge pump type booster circuit 21 is outputted via a drain of transistor Tn. Specifically, the drain of the transistor Tn serves as an output terminal of the charge pump type booster circuit 21.
Each of the capacitors C1 to Cn is embodied as a MOS capacitor formed of an NMOS transistor. A gate of each NMOS transistor forming one electrode of each of the capacitors C1 to Cn is connected to each of the nodes N1 to Nn. Moreover, for the capacitors C1 to Cn, a source and drain of each NMOS transistor forming the other electrode of each of the odd capacitors C1, C3 . . . C2m+1 are connected to a node `b` between the transistors DP2 and DN2 of the driver 26, while a source and drain of each NMOS transistor forming the other electrode of each of the even capacitors C2, C4 . . . C2m are connected to a node `a` between the transistors DP1 and DN1 of the driver 25.
The nodes N1 to Nn are connected to the gates of transistors T1 to Tn, respectively. The nodes N1 to Nn are connected to the power supply VDD via the transistors TD1 to TDn, and gates of transistors TD1 to TDn are also connected to the power supply VDD. Specifically, since the transistors T1 to Tn, TD1 to TDn are diode-connected, the sources of transistors T1 to Tn, TD1 to TDn serve as diode anodes, and the drains of transistors T1 to Tn, TD1 to TDn serve as diode cathodes.
Additionally, since a high voltage is applied to each of the NMOS transistors forming the transistors T1 to Tn, TD1 to TDn and the capacitors C1 to Cn, the NMOS transistors have high pressure resistant structures.
The operation of the prior art charge pump type booster circuit 21 will next be described.
FIG. 6 is a timing chart of the nodes `a`, `b` and control signals a-1, a-2, b-1, b-2 in one cycle.
Each driver 25, 26 forming the driver circuit 22 is of a tri-state type. For a time t1 and a time t2, the control signal a-1 is at a high level, the control signal a-2 is at a low level, each transistor DP1, DN1 is turned off, and the node `a` provides a high impedance. Moreover, for a time t3 and a time t4, the control signal b-1 is at a high level, the control signal b-2 is at a low level, each transistor DP2, DN2 is turned off, and the node `b` provides a high impedance.
First, in an initial condition, each transistor DP1, DP2 is off, while each transistor DN1, DN2 is on. Each node `a`, `b` is at the low level.
Subsequently, the control signal a-2 falls in order to turn off the transistor DN1, the control signal a-1 falls in order to turn on the transistor DP1, and the node `a` rises in response. In this case, the even capacitors C2, C4 . . . C2m connected to the node `a` are subjected to a positive coupling, and electric potentials of the even nodes N2, N4 . . . N2m are raised. Therefore, the even transistors T2, T4 . . . T2m are turned on, and a positive charge moves to the odd node N3, N5 . . . N2m+1, whose number advances by one from the even node N2, N4 . . . N2m.
After the control signal a-1 rises to turn off the transistor DP1, and the control signal a-2 rises to turn on the transistor DN1, the node `a` falls. In this case, the even capacitors C2, C4 . . . C2m connected to the node `a` are subjected to a negative coupling. Therefore, the electric potentials of even nodes N2, N4 . . . N2m are lowered.
Subsequently, the control signal b-2 falls in order to turn off the transistor DN2, the control signal b-1 falls in order to turn on the transistor DP2, and the node `b` rises in response. In this case, the odd capacitors C1, C3 . . . C2m+1 connected to the node `b` are subjected to the positive coupling, and the electric potentials of the odd nodes N1, N3 . . . N2m+1 are raised. Therefore, the odd transistors T1, T3 . . . T2m+1 are turned on, and the positive charge moves to the even node N2, N4 . . . N2m+2, whose number advances by one from the odd node N1, N3 . . . N2m+1.
After the control signal b-1 rises in order to turn off the transistor DP2, and the control signal b-2 rises in order to turn on the transistor DN2, the node `b` falls in response. In this case, the odd capacitors C1, C3 . . . C2m+1 connected to the node `b` are subjected to the negative coupling. Therefore, the electric potentials of the odd nodes N1, N3 . . . N2m+1 are lowered.
The aforementioned operation is repeatedly performed as one cycle.
When the coupling ratio of each of the capacitors C1 to Cn is and the threshold voltage of each of the transistors T1 to Tn and TD1 is Vt, the electric potentials of the nodes N2 to Nn are raised only by .alpha.VDD-Vt from the node less in number by one, i.e., N1 to Nn-1. Specifically, the voltage gain for each stage of the charge pump series 23 is .alpha.VDD-Vt.
For example, the original potential of the node N1 is an electric potential VDD-Vt, which is obtained by subtracting the threshold voltage Vt of the transistor TD1 from the power supply voltage VDD. Therefore, the electric potential of the node N2 is (.alpha.+1)VDD-2Vt, which is obtained by adding .alpha.VDD-Vt to the original potential VDD-Vt of the node N1. Similarly, the electric potential of the node N3 is (2.alpha.+1)VDD-3Vt, which is obtained by adding .alpha.VDD-Vt to the electric potential (.alpha.+1)VDD-2Vt of the node N2.
The charge pumping operation as described above sequentially moves the positive charge to the drain or output terminal of the transistor Tn from the power supply VDD in each stage of the charge pump series 23, and the electric potential is raised only by .alpha.VDD-Vt in each stage of the charge pump series 23. Therefore, a maximum value HVOUT(max) which can be reached by the output voltage HVOUT in the n stages of the charge pump series 23 is represented by following equation (1): EQU HVOUT(max)=(n.alpha.+1)VDD-(n+1)Vt (1)
Therefore, according to the charge pump type booster circuit 21, a desired positive potential output voltage HVOUT can be obtained by appropriately setting the number n of stages of the charge pump series 23.
Additionally, each of the transistors TD2 to TDn has a function of increasing the boosting rate, and further enhancing the boosting efficiency when .alpha.xVDD is small. Specifically, when the threshold voltage of each of the transistors TD2 to TDn is VT, the electric potential of each of the nodes N2 to Nn is initially VDD-VT by disposing the transistors TD2 to TDn as shown. On the other hand, when the transistors TD2 to TDn are omitted, the electric potential of each of the nodes N2 to Nn may be less than VDD-VT in the initial condition. Therefore, when the transistors TD2 to TDn are provided, the electric potentials of the nodes N2 to Nn can be made higher than VDD-VT after the boosting operation starts. Therefore, the transistors TD2 to TDn supply positive charges to the capacitors C1 to Cn.
When an EEPROM is erased, or "flashed", data in the entire memory cell array is deleted all at once, or the memory cell array is divided into arbitrary blocks, and the data deletion is performed in each block. The flash EEPROM is also called a flash memory, which can realize a large volume, low power consumption, and high-speed operation, and which is superior in shock resistance. Therefore, flash EEPROMs are ideal for use in various portable electronic apparatuses.
A certain type of flash EEPROM requires a negative potential for writing and deleting the data. In this type, the necessary negative potential is obtained by using the charge pump type booster circuit to boost the ground voltage (=0V) in a negative direction.
FIG. 7 shows a conventional charge pump type booster circuit for obtaining a negative booster voltage. In the charge pump type booster circuit shown in FIG. 7, elements the same as those in the charge pump type booster circuit 21 shown in FIG. 5 are denoted with the same reference characters, and a detailed description thereof is therefore omitted.
A charge pump type booster circuit 201 shown in FIG. 7 is different from the charge pump type booster circuit 21 shown in FIG. 5 in the following respects:
(a) Each of the transistors T1 to Tn, TD1 to TDn is formed of a PMOS transistor, instead of an NMOS transistor. Since a high voltage is applied to the PMOS transistor, the transistor has a high pressure resistant structure. PA1 (b) Each of the capacitors C1 to Cn is embodied as a MOS capacitor formed by a PMOS transistor, instead of a MOS capacitor formed by an NMOS transistor. PA1 (c) Each of the nodes N1 to Nn is connected to the ground via each of the PMOS transistors TD1 to TDn, and the gates of the PMOS transistors TD1 to TDn are also connected to the ground.
The operation of the charge pump type booster circuit 201 will next be described.
FIG. 8 is a timing chart of the nodes `a`, `b` and control signals a-1, a-2, b-1, b-2 in one cycle.
First, in the initial condition, each transistor DP1, DP2 is off, while each transistor DN1, DN2 is on. Each node `a`, `b` is at a high level.
Subsequently, the control signal a-1 rises in order to turn off the transistor DP1, the control signal a-2 rises in order to turn on the transistor DN1, and the node `a` falls in response. In this case, the even capacitors C2, C4 . . . C2m connected to the node `a` are subjected to the negative coupling, and the electric potentials of the even nodes N2, N4 . . . N2m are lowered. Therefore, the even transistors T2, T4 . . . T2m are turned on, and a negative charge moves to the odd node N3, N5 . . . N2m+1, whose number advances by one from the even nodes N2, N4 . . . N2m.
After the control signal a-2 falls in order to turn off the transistor DN1, and the control signal a-1 falls in order to turn on the transistor DP1, the node `a` rises. In this case, the even capacitors C2, C4 . . . C2m connected to the node `a` are subjected to the positive coupling. Therefore, the electric potentials of the even nodes N2, N4 . . . N2m are raised.
Subsequently, the control signal b-1 rises in order to turn off the transistor DP2, the control signal b-2 rises in order to turn on the transistor DN2, and the node `b` falls in response. In this case, the odd capacitors C1, C3 . . . C2m+1 connected to the node `b` are subjected to the negative coupling, and the electric potentials of the odd nodes N1, N3 . . . N2m+1 are lowered. Therefore, the odd transistors T1, T3 . . . T2m+1 are turned on, and the negative charge moves to the even nodes N2, N4 . . . N2m+2, whose number advances by one from the odd nodes N1, N3 . . . N2m+1.
After the control signal b-2 falls in order to turn off the transistor DN2, and the control signal b-1 falls in order to turn on the transistor DP2, the node `b` rises. In this case, the odd capacitors C1, C3 . . . C2m+1 connected to the node `b` are subjected to the positive coupling. Therefore, the electric potentials of the odd nodes N1, N3 . . . N2m+1 are raised.
When the aforementioned operation is repeatedly performed as one cycle, the electric potential of each of the nodes N2 to Nn is varied only by -.alpha.VDD+Vt from the electric potential of the previous node, i.e., N1 to Nn-1. Specifically, the voltage gain for each stage of the charge pump series 23 is -.alpha.VDD+Vt.
For example, the original potential of the node N1 is an electric potential 0V+Vt, which is obtained by adding the threshold voltage Vt of the transistor TD1 to the ground potential. Therefore, the electric potential of the node N2 is -.alpha.VDD+2Vt, which is a change of -.alpha.VDD+Vt from the original potential 0V+Vt of the node N1. Similarly, the electric potential of the node N3 is -2.alpha.VDD+3Vt, which is a change of -.alpha.VDD+Vt from the electric potential -.alpha.VDD+2Vt of the node N2.
The charge pumping operation as described above sequentially moves the negative charge to the drain or output terminal of the transistor Tn from the power supply VDD in each stage of the charge pump series 23, and the electric potential is lowered only by -.alpha.VDD+Vt in each stage of the charge pump series 23. Therefore, the maximum value HVOUT(max) which can be reached by the output voltage HVOUT in the n stages of the charge pump series 23 is represented by following equation (2): EQU HVOUT(max)=-n.alpha.VDD+(n+1)Vt (2)
Therefore, according to the charge pump type booster circuit 201, a desired negative output voltage HVOUT can be obtained by appropriately setting the number n of stages of the charge pump series 23.
Additionally, each of the transistors TD2 to TDn has a function of increasing the boosting rate, and further enhancing the boosting efficiency when .alpha.xVDD is small. Specifically, when the threshold voltage of each of the transistors TD2 to TDn is VT, by disposing the transistors TD2 to TDn as shown, the initial electric potential of each of the nodes N2 to Nn is VT. On the other hand, when the transistors TD2 to TDn are omitted, the electric potential of each of the nodes N2 to Nn may initially become higher than VT. Therefore, when the transistors TD2 to TDn are provided, the electric potential of each of the nodes N2 to Nn can be made lower than VT after the boosting operation starts. Therefore, the transistors TD2 to TDn supply negative charge to the capacitors C1 to Cn.
The power supply voltage VDD has heretofore generally been 5V, but recently it has been required to be lowered to 3.3V. Accordingly, in the charge pump type booster circuit 21 for obtaining a positive booster voltage, the number n of stages of the charge pump series 23 have been increased in order to obtain the necessary output voltage HVOUT from the low power supply voltage VDD.
Moreover, in the charge pump type booster circuit 201 for obtaining a negative booster voltage, the number n of stages of the charge pump series 23 also have to be increased in order to obtain a low negative potential.
In the prior art charge pump type booster circuit 21 or 201, when the number n of stages of the charge pump series 23 are increased, the charge/discharge currents of the capacitors C2 to Cn are increased. Therefore, a problem results in that the power consumption of the charge pump type booster circuit is enlarged.